A sense amplifier is an electronic circuit that senses a relatively small voltage differential and amplifies it to a stable and recognizable logic level. Sense amplifiers are used in various kinds of electronic circuitry, including computer memory. In static random-access memory (SRAM), for example, a sense amplifier may be associated with each column of an array of memory cells and configured to read the voltage differentials stored in the cells. In particular, a sense amplifier may be linked to the pair of complementary bit lines that run down each column of memory cells.
To provide high bit density and low power consumption, the transistors of an SRAM are extremely small, having a limited capacity to source and sink current. Nevertheless, the bit lines may present a significant capacitive load, such that during a read operation, the voltage differential stored in the selected cell does not appear instantly on the bit lines, but develops over some period of time. Accordingly, a sense amplifier that triggers on a smaller voltage differential will be able to expose the stored logic state earlier in the read cycle, thereby reducing access time for the SRAM. In practice, it is the input offset voltage (IOV) of a sense amplifier that determines the minimum voltage differential that can be sensed. Accordingly, it is desirable to minimize the IOV.
IOV in a sense-amplifier circuit arises mostly from variability in the transistors of the input stage of the circuit. This effect may be exacerbated by the deep sub-micro architecture of the state-of-the art complementary metal-oxide semiconductor (CMOS) process, which provides high-density, low-power SRAM. A straightforward approach to reducing IOV is upsizing the transistors of the sense amplifier. This approach is disadvantageous in SRAM applications, however, due to the chip area it requires. Other approaches include offset trimming and offset calibration on start-up. These approaches increase operational complexity in addition to requiring extra chip area.